Stacked DRAM, TSVs, and yield: why one good die is insufficient

A stack is a manufacturing chain

HBM gains density and interface width by placing DRAM dies vertically over a logic base die. Through-silicon vias (TSVs) are vertical conductors through silicon; bonding joins the layers. The base die manages signals and power, and the stack sits beside compute in an advanced package. Short paths and a wide interface help data movement, but the part now depends on die processing, thinning, alignment, bonding, test, thermal design, and package assembly.

1. 1known-good DRAM dies
2. 2TSV/thinning
3. 3align and bond
4. 4test stack
5. 5package with logic

1. 1die defects + bond defects + warpage + thermal limits
2. 2qualified-stack yield

Micron’s HBM3E brief lists eight-high and twelve-high variants: “high” counts vertical memory dies. Samsung describes an HBM4 mechanical test vehicle as a functional prototype for package setup, prequalification, and thermal pre-evaluation. That description is evidence of its own workflow, not a universal yield measurement.

Why yields compound

Yield is the fraction passing a named test at a named stage. Consider a toy model: eight selected dies each pass at 99.5%, and assembly plus final test passes at 98%. Assuming independence, 0.995^8 is about 96.1%; multiplying by 98% gives 94.2% final yield. At twelve dies, 0.995^12 is about 94.2% before assembly. These are invented inputs: failures can correlate, screening changes the population, repair and binning may exist, and real yields are confidential.

The math still shows why a capacity headline can stress stages beyond wafer starts. Sellable stacks need enough passing compatible dies, TSV and bonding capacity, substrates, assembly, final electrical and thermal qualification. Improving one stage does not guarantee output if another is limiting. Thinning helps vertical connections but makes handling delicate; thousands of connections need timing margin; power and heat must leave the compact stack. Test must find faults in the assembled configuration, not only in bare dies.

SK hynix and TSMC said in their 2024 announcement that they would collaborate on next-generation HBM, including logic base die and advanced packaging. That supports the dated collaboration claim, not allocations, prices, yield, or a customer shipment.

Exercise: sensitivity without false precision

Build a sheet with stack height, screened-die yield, assembly yield, and required qualified stacks. Use die_yield ^ stack_height × assembly_yield, label it illustrative, and vary one input at a time. Then add a nonnumeric checklist: thermal qualification, base-die availability, substrate, test capacity, and customer qualification. Write only: “if this stage limits supply, a one-point yield change has this modeled effect.” Do not convert the toy sheet into a company yield estimate.

Timing matters too. Finished dies cannot necessarily substitute freely: electrical bins, inventory age, assembly schedules, and customer qualification can control which material enters a stack. Reporting a high final yield without naming the input population also misleads; post-screening yield is not wafer yield. Pair the sheet with reliability evidence for thermal cycling, mechanical stress, signal margin, and error behavior. Passing initial function test is not long-term reliability, and neither is a product capacity point a cost or supply forecast.