REGISTERED TAG
Semiconductors
Explain semiconductor devices, interfaces, manufacturing, packaging and qualification.
Why HBM bandwidth matters: count bytes before FLOPS
Connect a kernel's arithmetic intensity to HBM bandwidth, capacity, and an honest performance experiment.
Stacked DRAM, TSVs, and yield: why one good die is insufficient
Follow an HBM stack through TSV interconnect, assembly, heat, test, and compounded yield.
HBM4 interfaces and packaging: more pins change the system
Understand a wider HBM4 interface, logic base die, package co-design, and the limits of multiplying pin speed.
SanDisk: the flash business after separation
Read SanDisk's standalone FY2026 reporting as a flash-storage business, while keeping pre-separation comparability limits visible.
Micron, HBM, and the difference between a part and a platform
Connect Micron's HBM3E product disclosures to an AI-system qualification chain without turning product claims into market facts.
Micron cash flow and capex: separate investment from a headline
Read a memory maker's earnings materials by keeping GAAP profit, operating cash flow, capital expenditure, and capacity effects distinct.
SK hynix memory economics: product leadership is not a margin model
Read SK hynix HBM announcements as product and supply-chain evidence, then build a separate, falsifiable economics model.
Samsung memory competition: compare qualification, architecture, and disclosure
Samsung’s memory position must be separated into DRAM, NAND, HBM qualification, packaging, and the economics disclosed by a diversified company.
Kioxia and Western Digital: NAND partnership, products, and accounting boundaries
Compare NAND businesses by wafer technology, joint manufacturing arrangements, client versus enterprise products, and the legal entity that reports the accounting.
Advanced packaging bottlenecks: why a known-good die is not a shippable accelerator
HBM demand is constrained by more than DRAM wafers: TSV processing, die stacking, base die, interposer or substrate, bonding, thermal paths, test, and system qualification all have yields.
Memory equipment suppliers: read process step exposure before calling capex leverage
Equipment revenue is exposed to process intensity and customer capital plans, but tool shipment, installed base service, and a memory maker’s bit output are different time series.
Micron FY2026: trace customer deposits separately from operating cash
Reconcile a memory maker's reported cash, investment and customer funding before drawing a capacity or valuation conclusion.
800G and 1.6T optics: a port rate is a budget
Read an 800G or 1.6T label through lanes, modulation, host loss, fiber reach, FEC, and qualification.
Transceivers, lasers, and DSPs: where an electrical lane becomes light
A module is an electrical, optical, thermal, and manufacturing chain. Map each conversion before attributing value or a failure.
Silicon photonics and CPO: shorten the electrical path, change the service model
Co-packaged optics moves the optical engine beside the switch ASIC. It can improve the electrical budget while changing assembly, cooling, and repair.
Broadcom and Marvell: where value sits between the switch and the optical module
A component-level guide to switch ASICs, optical DSPs and active-copper retimers: what each controls, what it does not prove, and how to test a value-capture thesis.
Optical supply chain: lasers, packaging, test, and qualification as bottlenecks
The next constraint may be an input, qualified process, test station, or customer validation. A shortage needs a named stage and evidence.