LEARNING PATH
MEMORY & SEMICONDUCTORS
Connect memory bandwidth, manufacturing, and semiconductor business economics.
Memory hierarchy for AI systems: locate the stalled byte
A concrete way to distinguish registers, cache, HBM/DRAM, SSD, and networked storage before making an infrastructure claim.
Why HBM bandwidth matters: count bytes before FLOPS
Connect a kernel's arithmetic intensity to HBM bandwidth, capacity, and an honest performance experiment.
Stacked DRAM, TSVs, and yield: why one good die is insufficient
Follow an HBM stack through TSV interconnect, assembly, heat, test, and compounded yield.
HBM4 interfaces and packaging: more pins change the system
Understand a wider HBM4 interface, logic base die, package co-design, and the limits of multiplying pin speed.
DRAM and NAND: two technologies, different cycles
Separate volatile working memory from persistent flash storage before making an AI-infrastructure or business claim.
NAND and SSD storage for AI: keep accelerators fed
Trace an AI data path through SSDs, host memory, decompression, and GPUs, including endurance and measurement limits.
SanDisk: the flash business after separation
Read SanDisk's standalone FY2026 reporting as a flash-storage business, while keeping pre-separation comparability limits visible.
SanDisk financial statements: turn revenue into cash carefully
Use the FY2026 GAAP income statement, cash flow statement, capital spending, and share counts without mixing periods or metrics.
SanDisk demand and pricing: separate exabytes from dollars
Use SanDisk's FY2026 end-market disclosures to distinguish volume, price, mix, and inventory explanations.
Micron, HBM, and the difference between a part and a platform
Connect Micron's HBM3E product disclosures to an AI-system qualification chain without turning product claims into market facts.
Micron cash flow and capex: separate investment from a headline
Read a memory maker's earnings materials by keeping GAAP profit, operating cash flow, capital expenditure, and capacity effects distinct.
SK hynix memory economics: product leadership is not a margin model
Read SK hynix HBM announcements as product and supply-chain evidence, then build a separate, falsifiable economics model.
Samsung memory competition: compare qualification, architecture, and disclosure
Samsung’s memory position must be separated into DRAM, NAND, HBM qualification, packaging, and the economics disclosed by a diversified company.
Kioxia and Western Digital: NAND partnership, products, and accounting boundaries
Compare NAND businesses by wafer technology, joint manufacturing arrangements, client versus enterprise products, and the legal entity that reports the accounting.
Advanced packaging bottlenecks: why a known-good die is not a shippable accelerator
HBM demand is constrained by more than DRAM wafers: TSV processing, die stacking, base die, interposer or substrate, bonding, thermal paths, test, and system qualification all have yields.
Memory equipment suppliers: read process step exposure before calling capex leverage
Equipment revenue is exposed to process intensity and customer capital plans, but tool shipment, installed base service, and a memory maker’s bit output are different time series.
Memory-cycle valuation: separate bit demand, pricing, utilization, and cash conversion
Memory cycles combine bit demand, supply additions, inventory, pricing, utilization, and capex. A valuation case should expose each driver and the date of the accounting evidence behind it.
Invalidating a memory thesis: design a dashboard that can change your mind
A serious memory thesis names its technical and financial disconfirming observations before it becomes a narrative. HBM, NAND, packaging, and equipment each fail differently.